During an ESD event, large currents can flow through an Integrated Circuit (IC), potentially causing damage to the IC. To avoid this damage, ESD protection circuits are added. In many ESD protection circuits, a chain of diodes is used. However, during very fast ESD events, a voltage overshoot is associated with every diode. When placing N diodes in series, this total overshoot is very high during the ESD event, which creates latch-up (dead short circuit between Vdd and ground), thus degrading or damaging sensitive nodes (e.g. gate oxides) in the circuitry.
A well-known approach to prevent latch up is to surround the diode(s) with a guard-band, which is, in the case of a P-substrate process, a heavily P-doped region. This will cause the current that is injected in the substrate to flow safely to the guard-band, which is generally connected to the ground. Thus, the guard-band isolates the diode from the outside circuitry. However, the P+ guard-band causes the triggering of the diode, and/or the diode chain to slow down.
Thus, there is a need in the art for a solution to provide an improved ESD protection device, which prevents any damage to the circuitry and also provides for an improved fast triggering during the ESD event.